Supplemenatry figures
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CIIC Harness
Table Of Contents
Description
Pinout description
General Purpose Input/Output
Housekeeping SPI
QSPI Flash interface
External clock
UART interface
SPI Master
Counter-Timers
Interrupts (IRQ)
SRAM
Programming
Memory Mapped I/O summary
Supplemenatry figures
Absolute maximum ratings
References
Further work
CIIC Harness
Table Of Contents
Description
Pinout description
General Purpose Input/Output
Housekeeping SPI
QSPI Flash interface
External clock
UART interface
SPI Master
Counter-Timers
Interrupts (IRQ)
SRAM
Programming
Memory Mapped I/O summary
Supplemenatry figures
Absolute maximum ratings
References
Further work
Supplemenatry figures
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GPIO pads - management and user IO
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GPIO pad structure - pads 0 (JTAG) and 1 (SDO)
¶
GPIO pad structure - all pads except 0 and 1
¶
Die arrangement and pads
¶
Die voltage clamp arrangement
¶
Die to WLCSP bond plan
¶
Power domain splits
¶
PCB example route pattern
¶
Table Of Contents
Supplemenatry figures
GPIO pads - management and user IO
GPIO pad structure - pads 0 (JTAG) and 1 (SDO)
GPIO pad structure - all pads except 0 and 1
Die arrangement and pads
Die voltage clamp arrangement
Die to WLCSP bond plan
Power domain splits
PCB example route pattern
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Memory Mapped I/O summary
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Absolute maximum ratings