Efabless Caravel “harness” SoC¶
Introduction¶
The efabless Caravel chip is a ready-to-use test harness for creating designs with the Google/Skywater 130nm Open PDK. The Caravel harness comprises a small RISC-V microprocessor based on the simple 2-cycle PicoRV32 RISC-V core implementing the RV32IMC instruction set (see riscv.org page), a 32-bit wishbone bus, and an approximately 2.8mm x 2.8mm open area for the placement of user IP blocks.
Fig. 1 Caravel management SoC simplified block diagram¶
The documentation contains the following chapters:
Description contains the general information about the Efabless Caravel “harness” SoC,
Pinout description describes the pinout of the SoC,
General Purpose Input/Output describes GPIO and its registers,
Housekeeping SPI describes the SPI slave that can be accessed from a remote host,
QSPI Flash interface describes the QSPI flash controller,
External clock describes the source external clock for the CPU,
UART interface describes the UART interface,
SPI Master describes the SPI configuration,
Counter-Timers describes two counter/timers blocks,
Interrupts (IRQ) describes the interrups,
SRAM describes management and storage area SRAM,
Programming shows how to get started with programming on Caravel chip,
Memory Mapped I/O summary lists the memory mapped I/O registers by address,
Supplementary figures provides supplementary internal structure and die arrangement figures
Absolute maximum ratings lists the parameters and their ranges at which the device operates correctly,
References contains list of references,
Further work lists things to be added to the documentation.
Fig. 14 Caravel harness die (3.2 mm x 5.3 mm)¶